Semiconductor integrated circuit devices typically include conductive layers, e.g., metal layers, separated by nonconductive layers. Conductive via plugs disposed in vias of an integrated circuit device usually interconnect conductive layers within the circuit device. For some applications, via plugs extend into active areas of an integrated circuit device to connect the active areas to contacts or wiring layers adjacent an exterior of the device.
One method of forming via plugs involves blanketing a nonmetal layer, such as a dielectric layer, of an integrated circuit device with a metal layer so that the metal fills vias disposed in the nonmetal layer. The metal layer is usually formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) (or sputtering), electroless plating, electroplating, etc. Excess metal overlying the dielectric layer is removed, such as by chemical-mechanical planarization (CMP), to define the via plugs. This is a complicated and time-consuming, and thus expensive, process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods for forming via plugs.